1. Field of the Invention
The present invention relates to a method for fabricating capacitors of a semiconductor device, and more particularly to a method for fabricating capacitors having an increased storage electrode surface area to enable the fabrication of highly integrated semiconductor devices.
2. Description of the Prior Art
The recent high integration trend of semiconductor devices inevitably involves a reduction in cell dimension. However, such a reduction in cell dimension results in a difficulty to form capacitors having a sufficient capacitance. This is because the capacitance is proportional to the surface area of the capacitor. In a case of a dynamic random access memory (DRAM) device constituted by one metal oxide semiconductor (MOS) transistor and one capacitor, in particular, it is important to reduce the area occupied by the capacitor and yet obtain a high capacitance of the capacitor, for the high integration of the DRAM device.
For increasing the capacitance, various research has been conducted. For example, there have been known use of a dielectric material exhibiting a high dielectric constant, formation of a thin dielectric film, and formation of capacitors having an increased surface area, taking into consideration the fact that the capacitance of the capacitor is proportional to the area of the capacitor and inversely proportional to the thickness of the dielectric film constituting the capacitor.
However, all of these methods have their own problems. Although various materials, such as Ta.sub.2 O.sub.5, TiO.sub.2 Or SrTiO.sub.3, have been proposed as the dielectric material exhibiting a high dielectric constant, their reliance and thin film characteristics have not been confirmed. For this reason, it is difficult to use such dielectric materials for semiconductor devices in practical situations, The reduction in the thickness of dielectric film results in damage to the dielectric film severely affecting the reliance of the capacitor.
In order to increase the surface area of the capacitor, various capacitor structures have also been proposed. They include a pin structure extending throughout a multi-layer polysilicon structure to connect the layers with one another, a labyrinthine structure with a cylindrical or rectangular shape, and a structure having hemispherical grains of silicon on a storage electrode surface. In these capacitor structures, however, the capacitance is still insufficient because the surface area of the capacitor is still small due to its reduction caused by the high integration of DRAM.
Now, a capacitor having the pin structure will be described in conjunction with FIGS. 1A to 1C respectively illustrating sequential steps of a conventional method for fabricating a semiconductor device.
In accordance with this method, a semiconductor substrate 31 is prepared and then metal oxide semiconductor (MOS) transistor structures are formed on the semiconductor substrate 31, as shown in FIG. 1A. Each MOS transistor structure includes an element-isolating oxide film 32, a gate oxide film 33, a gate electrode 34 and an impurity-diffused region 35. Thereafter, an interlayer insulating film 36 and a bit line 37 are formed. Over the resulting structure, a lower insulating layer 38 is then formed. The bit line 37 may be formed after forming the capacitor. A desired portion of the lower insulating layer 38 is then etched using a contact mask (not shown), thereby forming a contact hole 39. Over the resulting structure, a first polysilicon film 40 and an oxide film 41 are sequentially formed.
The oxide film 41 is also called a sacrificial film because it is removed after the formation of a storage electrode (not shown). The first polysilicon film 40 is a conduction layer made of polycide or the like.
Using a contact mask (not shown), the portion of the oxide film 41 disposed in the contact hole 39 is then anisotropically etched so that the first polysilicon film 40 will be exposed at its desired portion, as shown in FIG. 1B. Over the resulting structure, a second polysilicon film 42 is then formed to a desired thickness.
The second polysilicon film 42 is a conduction layer made of polycide or the like.
Subsequently, the second polysilicon film 42, oxide film 41 and first polysilicon film 40 are partially etched in a sequential manner using a storage electrode mask (not shown), as shown in FIG. 1C. At this etching step using the storage electrode mask, the lower insulating layer 38 is used as an etch barrier layer. The oxide film 41 is then completely removed in accordance with a wet etch method using the difference of the etch selectivity ratio between the first and second polysilicon films 40 and 42, thereby forming a pin-shaped storage electrode.
Although this pin-shaped storage electrode fabricated in accordance with the above-mentioned method has an improvement in topology, as compared to other type capacitors, this method involves a difficulty to ensure a sufficient capacitance for highly integrated semiconductor devices.